The present disclosure relates to a semiconductor structure, and particularly to field effect transistors including epitaxial active regions configured to avoid electrical shorts and a method of manufacturing the same.
Typically, formation of epitaxial source regions and epitaxial drain regions on field effect transistors is performed after patterning gate structures and forming gate spacers. The epitaxial source regions and epitaxial drain regions are formed by a selective epitaxial deposition process such that the epitaxial source regions and the epitaxial drain regions grow only from semiconductor surfaces of source regions and drain regions.
Because semiconductor devices are formed in high density with minimal spacing between adjacent devices and between each pair of a source region and a drain region in a same field effect transistor, process variations during the selective epitaxial deposition process can induce undesirable electrical shorts. Specifically, a higher deposition rate of a deposited semiconductor material during the selective epitaxy deposition process can cause epitaxial source regions and epitaxial drain regions to grow by more than a target thickness, and to undesirably merge with another epitaxial source region or another drain region.